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High Speed Synchronous Power MOSFET Smart Driver
POWER MANAGEMENT Description
The SC1405D is a Dual-MOSFET Driver with an internal Overlap Protection Circuit to prevent shoot-through. Each driver is capable of driving a 3000pF load in 15ns rise/ fall time and has ULTRA-LOW propagation delay from input transition to the gate of the power FETs. Adaptive Overlap Protection circuit ensures that the synchronous FET does not turn on until the top FET source has reached a voltage low enough to prevent shoot-through. The delay between the bottom gate going low to the top gate transitioning high is externally programmable via a capacitor to minimize dead time. The bottom FET may be disabled at light loads by keeping S_MOD low to trigger asynchronous operation, thus saving the bottom FET's gate drive current and inductor ripple current. An internal voltage reference allows threshold adjustment for an Output Over-Voltage protection circuitry, independent of the PWM controller. The device provides overvoltage protection independent of the PWM feedback loop with a unique "adaptive OVP" comparator which rejects noise but responds quickly to a true OVP situation. Under-Voltage-Lock-Out circuit is included to guarantee that both driver outputs are off when Vcc is less than or equal to 4.5V (typ) at supply ramp up (4.35V at supply ramp down). A CMOS output provides status indication of the 5V supply. A low enable input places the IC in standby mode, reducing supply current to less than 10A.
SC1405D
Features
Fast rise and fall times (15ns withPRELIMINARY 3000pf load) 14ns max. Propagation delay (BG going with low) Adaptive and programmable shoot-through protection Adaptive overvoltage protection Wide input voltage range (4.5-25V) Programmable delay between FETs Power saving asynchronous mode control Output overvoltage protection/overtemp shutdown Under-Voltage lock-out and power ready signal Less than 10A stand-by current (EN=low) Power ready output signal High frequency (to 1.2MHz) operation allows use of small inductors and low cost caps in place of electrolytics TSSOP-14 and SOIC-8 EDP package
Applications
High Density/Fast transient microprocessor power supplies Motor Drives/Class-D amps High efficiency portable computers
Typical Application Circuit
Revision: April 25, 2005
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SC1405D
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter VCC Supply Voltage BST to PGND BST to DRN DRN to PGND DRN to PGND OVP_S to PGND EN, CO, DSPS, MODE, PRDY , DELAY to AGND AGND to PGND Continuous Power Dissipation Thermal Impedance Junction to Case Thermal Impedance Junction to Ambient Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
NOTE: (1) Specification refers to application circuit.
Symbol VCCMAX VMAXBST-PGND VMAXBST-DRN VMAXDRN-PGN VMAXDRN-PGN VMAXOVP S-PGND
Conditions
Minimum -0.3 -0.3 -0.3
Maximum 7 30 8 25 25 10 VCC + 0.3 +1 0.66 2.56 40 150
Units V V V V V V V V C/W C/W C C C
DC Transient, 100nS
-2 -4 -0.3 -0.3 -1
Pd J C J A TJ TSTG TLEAD
Tamb = 25C, TJ = 125C Tcase = 25C, TJ = 125C
-40 -65
+125 +150 300
Electrical Characteristics - DC Operating Specifications
Unless specified: -40 < J < 125C; VCC = 5V; 4V < VBST < 26V
Parameter Pow er Supply Supply Voltage Quiescent Current Quiescent Current, operating PR D Y High Level Output Voltage Low Level Output Voltage Sink Current
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Symbol
Conditions
Min
Typ
Max
Units
V CC Iq_stby Iq_op E N = 0V VCC = 5V, CO = 0V
4.5
5
6.0 10
V A mA
1
VOH VOL IO_SINK
VCC = 4.7V, lload = 10mA VCC < UVLO threshold, lload = 10A VPRDY = 0.4V
2
4.5
4.55 0.1 0.2
V V mA
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SC1405D
POWER MANAGEMENT Electrical Characteristics - DC Operating Specifications
Parameter D S P S _D R High Level Output Voltage Low Level Output Voltage Under Voltage Lockout Start Threshold Hysteresis Logic Active Threshold Overvoltage Protection Trip Threshold Hysteresis Trip Delay, 50mV Overdrive Trip Delay, 100mV Overdrive S_MOD High Level Input Voltage Low Level Input Voltage Enable High Level Input Voltage Low Level Input Voltage CO High Level Input Voltage Low Level Input Voltage Thermal Shutdow n Over Temperature Trip Point Hysteresis High-Side Driver Peak Output Current Output Resistance IPKH RsrcTG RsinkTG Low -Side Drive Peak Output Current Output Resistance IPKL RsrcBG RsinkBG
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Symbol
Conditions
Min
Typ
Max
Units
VOH VOL
VCC = 4.6V, Cload = 100pF VCC = 4.6V, Cload = 100pF
4.15 0.05
V V
4.3 Vhys EN is low
4.5 0.05
4.7
V V
1.5
V
VTRIP VhysOVP t = 0 to 125oC t = 0 to 125oC
1.17
1.225 0.8
1.28
V V
300 125
470 225
800 400
ns ns
VIH VIL VIH VIL VIH VIL TOTP THYST
2.0 0.8 2.0 0.8 2.0 0.8 165 10
V V V V V V C C
o o
3 duty cycle < 2%, tpw < 100s, TJ = 125C, VBST - VDRN = 4.5V, VTG = 4.0V (src)+VDRN or VTG = 0.5V (sink)+VDRN 1 .7
A
3 duty cycle < 2%, tpw < 100s, TJ = 125C, VV S = 4.6V, VBG = 4V (src) or VLOWDR = 0.5V (sink)
3
A
1.2
1.0
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SC1405D
POWER MANAGEMENT Electrical Characteristics - AC Operating Specifications
Parameter High Side Driver rise time fall time propagation delay time, TG going high propagation delay time, TG going low Low -Side Driver rise time fall time propagation delay time, BG going high propagation delay time, TG going low Under-Voltage Lockout V_5 ramping up V_5 ramping down PR D Y EN is transitioning from low to high tpdhPRDY V_5 >UVLO threshold, Delay measured from EN > 2.0V to PRDY > 3.5V V_5 >UVLO threshold, Delay measured from EN < 0.8V to PRDY < 10% of V_5V 10 s tpdhUVLO tpdhUVLO EN is High EN is High 10 10 us us trBG trBG tpdhBGHI tpdlBG CI = 3nF, V CI = 3nF, V
VS
Symbol
Conditions
Min
Typ
Max
Units
trTG1 tfTG tpdhTG tpdlTG
CI = 3nF, VBST - VDRN = 4.6V, CI = 3nF, VBST - VDRN = 4.6V, CI = 3nF, VBST - VDRN = 4.6V, C-delay=0 CI = 3nF, VBST - VDRN = 4.6V,
14 12 20 15
23 19 32 24
ns ns ns ns
= 4.6V, = 4.6V,
15 13 12 7
24 21 19 12
ns ns ns ns
VS
CI = 3nF, VBST - VDRN = 4.6V, C-delay=0 CI = 3nF, V V S = 4.6V, DRN <1V
EN is transitioning fro high to low D S P S _D R rise/fall time propagation delay, DSPS_DR going high propagation delay, DSPS_DR goes low
tpdhUVLO
500
s
trDSPS DR. tpdhDSPS DR tpdlDSPS DR
CI = 100 pf, V_5 = 4.6V S_MOD goes high and BG goes high or S_MOD goes low S_MOD goes high and BG goes low
20 10 10
ns ns ns
NOTE: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC1405D
POWER MANAGEMENT Application Circuit - TSSOP-14
INPUT POWER + D1 1N 5819 8 3 << >> P_READ Y PW IN M (20KH z-1MH z) 47pF 7 2 4 6 1 5 Vcc GN D BST 14 13 12 9 11 10 2.2 2.2 MTB75N 03 75A,30V + + + + + MTB75N 03 75A,30V
+5V 10uF,6.3V + .1uF
.22uF
TG PR Y D EN DR N CO D ELAY_C BG OVP_S DSPS_D R S_MOD PGN D SC 1405
<<
DSPS_D R
Over-Voltage Sense
<<< Output Feedback to PWM Controller
Application Circuit - SOIC-8 EDP
Timing Diagram
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SC1405D
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Device SC1405DITSTRT P ackag e TSSOP-14 Temp Range (TJ) -40 to 125C
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
(14-Pin TSSOP)
Pin Descriptions
Pin # 1 2 3 4 5 6 Pin Name OVP_S EN GND CO S_MOD DELAY_C Pin Function Overvoltage protection sense. External scaling resistors required to set protection threshold. When high, this pin enables the internal circuitry of the device. When low, TG, BG, and PRDY are forced low and the supply current (5V) is less than 10A. Logic GND. TTL-level input signal to the MOSFET drivers. When low, this signal forces BG to be low, triggering asynchronous operation. When high, BG is not a function of this signal. The capacitance connected between this pin and GND sets the additional propagation delay for BG going low to TG going high. Total propagation delay =20ns + 1ns/pF. If no capacitor is connected, the propragation delay = 20ns. This pin indicates the status of VCC. When VCC is less than the UVLO threshold, this output is driven low. When VCC is greater than or equals to the UVLO threshold this output goes high. Input supply of 5 - 8V. A .22-1F ceramic capacitor should be connected from VCC to PGND very close to the chip. Output drive for the synchrounous (bottom) MOSFET. Power ground. Connect to the synchronous FET source pin (power ground). Dynamic Set Point Switch Drive. TTL level output signal. When S-MOD is high, this pin follows the BG driver pin voltage. This pin connects to the junction of the switching and synchronous MOSFET's. This pin can be subjected to a -2V minimum relative to PGND without affecting operation. Output gate drive for the switching (high-side) MOSFET. Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1F and 1F (ceramic).
7
PRDY
8 9 10 11 12 13 14
VC C BG PGND D S P S _D R DRN TG BST
NOTE: (1) All logic level inputs and outputs are open collector TTL compatible.
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SC1405D
POWER MANAGEMENT Pin Configuration Ordering Information
Device P ackag e SOIC-8 EDP Temp Range (TJ) -40 to 125C SC1405DISTRT
TOP VIEW
DRN TG BST EN BOTTOM 1 2 3 4 8 7 6 5 9 NAME GND BG VCC CO
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
(POWER SO-8)
Pin Descriptions
Pin # 1 2 3 Pin Name DRN TG BST Pin Function This pin connects to the junction of the switching and synchronous MOSFETs. This pin can be subjected to a -2V minimum relative to PGND without affecting operation. Output gate drive for the switching (high-side) MOSFET. Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1F and 1F (ceramic). When high, this pin enables the internal circuitry of the device. When low, TG and BG are forced low and the supply current (5V) is less than 10A. TTL-level input signal to the MOSFET drivers. +5V supply. A .22-1F ceramic capacitor should be connected from 5V to GND very close to this pin. Output drive for the synchronous (bottom) MOSFET. Ground. Pad is for heatsinking purpose. Connect to ground plane using multiple vias. Not electrically connected internally.
4 5 6 7 8 9
EN CO VC C BG GND THERMAL PAD
NOTE: (1) All logic level inputs and outputs are open collector TTL compatible.
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SC1405D
POWER MANAGEMENT Block Diagram
Applications Information
SC1405D is designed to drive Low Rds_On power FETs with ultra-low rise/fall times and propagation delays. As the switching frequency of PWM controllers is increased to reduce power supply volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP FET) and reduce Dead-time (BOTTOM FET) losses. While Low Rds_On FETs present a power saving in I2R losses, the FET's die area is larger and thus the effective input capacitance of the FET is increased. Often a 50% decrease in Rds_On more than doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and dead-time losses with a suboptimum driver. While discrete solution can achieve reasonable drive capability, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe operation can become cumbersome and costly. The SC1405 family of parts presents a total solution for the highspeed, high power density applications. Wide input supply range of 4.5V-25V allows use in battery powered applications, new high voltage, distributed power servers as well as Class-D amplifiers. Theory of Operation The control input (CO) to the SC1405D is typically supplied by a PWM controller that regulates the power supply output. (See Application Evaluation Schematic, Figure 3). The timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. The shoot-through protection is imple 2005 Semtech Corp. 8
mented by holding the bottom FET off until the voltage at the phase node (intersection of top FET source, the output inductor and the bottom FET's drain) has dropped below 1V. This assures that the top FET has turned off and that a direct current path does not exist between the input supply and ground, a condition which both the top and bottom FETs are on momentarily. The top FET is also prevented from turning on until the bottom FET is off. This time is internally set to 20ns (typical) and may be increased by adding a capacitor from the C-Delay pin to GND. The delay is approximately 1ns/pF in addition to the internal 20ns delay. The external capacitor may be needed if multiple High input capacitance FETs are used in parallel and the fall time is substantially greater than 20ns. It must be noted that increasing the dead-time by high values of C-Delay capacitor will reduce efficiency since the parallel Schottky or the bottom FET's body diode will have to conduct during dead-time. Layout Guidelines As with any high speed , high current circuit, proper layout is critical in achieving optimum performance of the SC1405D. The Evaluation board schematic (Refer to figure 3) shows a dual phase synchronous design with all surface mountable components. While components connecting to C-Delay, OVP_S, EN,SMOD, DSPS_DR and PRDY are relatively noncritical, tight
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SC1405D
POWER MANAGEMENT Applications Information
placement and short, wide traces must be used in layout of The Drives, DRN, and especially PGND pin. The top gate driver supply voltage is provided by bootstrapping the +5V supply and adding it the phase node voltage (DRN). Since the bootstrap capacitor supplies the charge to the TOP gate, it must be less than 0.5" away from the SC1405. Ceramic X7R capacitors are a good choice for supply bypassing near the chip. The Vcc pin capacitor must also be less than 0.5" away from the SC1405. The ground node of this capacitor, the SC1405 PGND pin and the Source of the bottom FET must be very close to each other, preferably with common PCB copper land and multiple vias to the ground plane (if used). The parallel Schottky (if used) must be physically next to the Bottom FET's drain and source. Any trace or lead inductance in these connections will drive current way from the Schottky and allow it to flow through the FET's body diode, thus reducing efficiency. Preventing Inadvertent Bottom FET Turn-on At high input voltages, (12V and greater) a fast turn-on of the top FET creates a positive going spike on the Bottom FET's gate through the Miller capacitance, Crss of the bottom FET. The voltage appearing on the gate due to this spike is: Vspike= Vin*crss (Crass+ciss) Where Ciss is the input gate capacitance of the bottom FET. This is assuming that the impedance of the drive path is too high compared to the instantaneous impedance of the capacitors. (since dV/dT and thus the effective frequency is very high). If the BG pin of the SC1405D is very close to the bottom FET, Vspike will be reduced depending on trace inductance, rate if rise of current, etc. While not shown in Figure 3, a capacitor may be added from the gate of the bottom FET to its source, preferably less than 0.5" away. This capacitor will be added to Ciss in the above equation to reduce the effective spike voltage, Vspike. The selection of the bottom FET must be done with attention paid to the Crss/Ciss ratio. A low ratio reduces the Miller feedback and thus reduces Vspike. Also FETs
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with higher Turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. The FET shown in the schematic has a 2 volt threshold and will require approximately 5 volts Vgs to be conducting, thus reducing the possibility of shoot-through. A zero ohm bottom FET gate resistor will obviously help keeping the gate voltage low. Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low. Ringing on the Phase Node The top FET source must be close to the bottom FET drain to prevent ringing and the possibility of the phase node going negative. This frequency is determined by: 1 Fring = (2 * Sqrt(Lst*Coss)) Where: Lst = The effective stray inductance of the top FET added to trace inductance of the connection between top FET's source and the bottom FET's drain added to the trace resistance of the bottom FET's ground connection. Coss=Drain to source capacitance of bottom FET. If there is a Schottky used, the capacitance of the Schottky is added to the value. Although this ringing does not pose any power losses due to a fairly high Q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. This ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 1000-2000pf, in parallel with Coss can often eliminate the EMI issue. If double pulsing is caused due to excessive ringing, placing 4.7-10 ohm resistor between the phase node and the DRN pin of the SC1405 should eliminate the double pulsing. The negative voltage spikes on the phase node adds to the bootstrap capacitor voltage, thus increasing the voltage between VBST - VDRN. If the phase node negative spikes are too large, the voltage on the boost capacitor could exceed device's absolute maximum rating of 8V.
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SC1405D
POWER MANAGEMENT Applications Information (Cont.)
To eliminate the effect of the ringing on the boost capacitor voltage, place a 4.7 - 10 Ohm resistor between boost Schottky diode and Vcc to filter the negative spikes on DRN Pin. Alternately, a Silicon diode, such as the commonly available 1N4148 can substitute for the Schottky diode and eliminate the need for the series resistor. Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of SO-8 or other surface mount FETs will reduce lead inductance and their parasitic effects. ASYNCHRONOUS OPERATION The SC1405D can be configured to operate in Asynchronous mode by pulling S-MOD to logic LOW, thus disabling the bottom FET drive. This has the effect of saving power at light loads since the bottom FET's gate capacitance does not have to charged at the switching frequency. There can be a significant savings since the bottom driver can supply up to 2A pulses to the FET at the switching frequency. There is an additional efficiency benefit to operating in asynchronous mode. When operating in synchronous mode, the inductor current can go negative and flow in reverse direction when the bottom FET is on and the DC load is less than 1/2 inductor ripple current. At that point, the inductor core and wire losses, depending on the magnitude of the ripple current, can be quite significant. Operating in asynchronous mode at light loads effectively only charges the inductor by as much as needed to supply the load current, since the inductor never completely discharges at light loads. DC regulation can be an issue when operating in asynchronous mode, depending on the type of controller used and minimum load required to maintain regulation. If there are no Shottkey diodes used in parallel with bottom FET, the FET's body diode will need to conduct in asynchronous mode. The high voltage drop of this diode must be considered when determining the criteria for this mode of operation. DSPS DR This pin produces an output which is a logical duplicate of the bottom FET's gate drive, if S-MOD is held LOW. OVP_S/OVER TEMP SHUTDOWN Output over-voltage protection (OVP) may be implemented on the SC1405D independent of the PWM controller . A voltage divider from the output is compared with the internal bandgap voltage of 1.2V (typical). Upon exceeding this voltage, the overvoltage comparator disables the top FET, while turning on the bottom FET to allow discharge of the output capacitors excessive voltage through the output inductor. The SC1405D has a unique adaptive OVP circuit. Short noise pulses, less than ~100ns are rejected completely; longer pulses will trigger OVP if only of sufficient magnitude. A long term transient will trigger OVP with a smaller magnitude. To assure proper tripping, bypass the resistor from OVP_S pin to GND with a capacitor. The value of this capacitor must be selected to achieve a time constant equal to one switching period. Leave at least 250mV headroom on the OVP pin to prevent false OVP events. The SC1405D will shutdown if its TJ exceeds 165C.
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SC1405D
POWER MANAGEMENT Typical Characteristics
Performance diagrams, Application Evaluation Board.
PIN Descriptions PIN Descriptions
Timing diagram: Ch1: CO input Ch2: TG drive Ch3: BG non-overlap drive Ch4: phase node Iout = 20A (10A/phase) Refer to Eval. Schematic (fig.3)
Timing diagram: Rise/Fall times Ch1: TG drive Ch2: BG drive Cursor: TpdhTG Iout = 20A (10A/phase) Refer to Eval. Schematic (fig.3)
VIN = 12V, VOUT = 1.6V. Top FET = IR7811 FDB7030(BL) Qgd = 23nc
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SC1405D
POWER MANAGEMENT Typical Characteristics (Cont.)
SC1405D OVP Delay vs. Temperature
600.00
500.00
400.00 Delay (nS)
300.00
200.00
100.00
0.00 -25 -5 15 35 55 Temperature (C) 50mV Overdrive 100mV Overdrive 75 95 115 135
Typical Delay vs. Overdrive (T=25C)
10000
Delay (nS)
1000
100 10 Overdrive (mV) 1000
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SC1405D
POWER MANAGEMENT Outline Drawing -TSSOP-14
Land Pattern - TSSOP-14
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SC1405D
POWER MANAGEMENT Outline Drawing - Power SOIC-8L
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SC1405D
POWER MANAGEMENT Land Pattern - Power SOIC-8L
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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